receiver clock out (20 to 85mhz) - 1 - 85mhz lvds 18 bit color host-lcd panel interface general description the THC63LVDM63A transmitter converts 21 bits of cmos/ttl data into lvds(low voltage differential signaling) data stream. a phase-locked transmit clock is transmitted in parallel with the data streams over a fourth lvds link. the THC63LVDM63A can be programmed for rising edge or falling edge clocks through a dedicated pin. the thc63lvdf64a receiver convert the lvds data streams back into 21 bits of cmos/ttl data with falling edge clock. at a transmit clock frequency of 85mhz, 18 bits of rgb data and 3 bits of lcd timing and control data (hsync, vsync, cntl1) are transmitted at a rate of 595 mbps per lvds dat a channel. features 21:3 data channel compression at up to 223 megabytes per sec throughput wide frequency range: 20 - 85 mhz suited for vga,svga,xga and sxga narrow bus (8 lines) reduces cable size 345mv swing lvds devices for low emi supports spread spectrum clock generator on chip input jitter filtering pll requires no external components single 3.3v supply with 110mw(typ) low power cmos design power-down mode low profile 48 lead tssop package clock edge programmable for transmitter improved replacement for the national ds90cf363/364 thine preliminary THC63LVDM63A/thc63lvdf64a pll transmitter clk in (20 to 85mhz) r/f 7 /pdwn data (lvds) (140 to 595 mbit/ on each lvds channel) clock (lvds) (20 to 85mhz) cmos/ttl inputs cmos/ttl outputs THC63LVDM63A pll thc63lvdf64a ta0- 6 7 tb0-6 tc0-6 7 7
- 2 - 0.5 typ 1.2 max (1.0) 0.10 ?0.05 48 lead molded thin shrink small outline package, jedec unit: millimeter s thc63lvdf64a pin out THC63LVDM63A package thine 1 24 4.05 6.1 ?0.1 12.5 ?0.1 48 25 transmitter device receiver device 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vcc rc2 rc1 rc0 gnd rb6 vcc rb5 rb4 rb3 gnd rb2 vcc rb1 rb0 ra6 gnd ra5 ra4 ra3 vcc ra2 ra1 gnd rc3 rc4 gnd rc5 rc6 n/c lvds gnd ra- ra+ rb- rb+ lvds vcc lvds gnd rc- rc+ rclk- rclk+ lvds gnd pll gnd pll vcc pll gnd /pdwn clkout ra0 ta4 vcc ta5 ta6 gnd tb0 tb1 vcc tb2 tb3 gnd tb4 tb5 r/f tb6 tc0 gnd tc1 tc2 tc3 vcc tc4 tc5 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ta3 ta2 gnd ta1 ta0 n/c lvds gnd ta- ta+ tb- tb+ lvds vcc lvds gnd tc- tc+ tclk- tclk+ lvds gnd pll gnd pll vcc pll gnd /pdwn clk in tc6 8.1 ?0.1 0.20 typ
symbol parameter conditions min typ max units v ih high level input voltage 2.0 vcc v v il low level input voltage gnd 0.8 v v oh high level output voltage i oh =-4ma 2.4 v v ol low level output voltage i ol =4ma 0.4 v i in input current 0v v in vcc ?10 ? i pd pull down current r/f pin,v ih =vcc 100 ? i os output short circuit current v out =0v -50 ? - 3 - v od differential output voltage rl=100 w 250 350 450 mv d v od change in vod between 35 mv complimentary output states v oc common mode voltage 1.125 1.25 1.375 v d v oc change in voc between 35 mv complimentary output states i os output short circuit current v out =0v,rl=100 w -24 ma i oz output tri-state current /pdwn=0v, ?0 ? v out =0v to vcc v th differential input high threshold v oc =+1.2v +100 mv v tl differential input low threshold -100 mv i in input current v in =+2.4v/ 0v ?0 ? vcc=3.6v absolute maximum ratings (note 1) supply voltage (vcc) -0.3 to +4v cmos/ttl input voltage -0.3v to (vcc + 0.3v) cmos/ttl output voltage -0.3v to (vcc + 0.3v) lvds receiver input voltage -0.3v to (vcc + 0.3v) lvds driver output voltage -0.3v to (vcc + 0.3v) output short circuit duration continuous junction temperature +150?c storage temperature range -65?c to 150?c lead temperature(soldering, 4 sec.) +260?c maximum power dissipation @25?c 1.4w electrical characteristics vcc = 3.0 - 3.6v, ta = -10 - +70 ?c cmos/ttl dc specifications lvds driver dc specifications note 1:"absolute maximum ratings" are those values beyond which the safety of the device cannot be guaranteed. they are not ment to imply that the device should be operated at these limits. the tables of "electrical characteristics" specify conditions for device operation. thine lvds receiver dc specifications
thine supply current vcc = 3.0 - 3.6v, ta = -10 - +70 ?c - 4 - tx0/rx 0 tx1/rx 1 tx2/rx 2 tx3/rx 3 tx4/rx 4 clk i n tx5/rx 5 tx6/rx 6 16 grayscale pattern even txin/rxin clk i n worst case pattern odd txin/rxin symbol parameter conditions typ max units i tccg transmitter supply current rl=100 w ,cl=5pf, vcc=3.3v, 16 grayscale pattern f=65mhz f=85mhz 33 41 ma 37 45 ma i tccw transmitter supply current rl=100 w ,cl=5pf, vcc=3.3v, worst case pattern f=65mhz f=85mhz 35 43 ma 39 47 ma i tccs transmitter power down supply current /pdwn =0 v 10 ? i rccg receiver supply current cl=8pf, vcc=3.3v, 16 grayscale pattern f=65mhz f=85mhz 33 43 ma 44 54 ma i rccw receiver supply current cl=8pf, vcc=3.3v, worst case pattern f=65mhz f=85mhz 58 75 ma 70 87 ma i rccs receiver power down supply current /pdwn =0 v 10 ?
thine switching characteristics vcc = 3.0 - 3.6v, ta = -10 - +70 ?c symbol parameter min typ max units transmitter t tcit clk in transition time 5.0 ns t tcp clk in period 11.76 t 50.0 ns t tch clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/- delay 2t/7 ns t ts ttl data setup to clk in 2.5 ns t th ttl data hold from clk in 2.5 ns t lvt lvds transition time 0.6 1.5 ns t top1 output data position 0 (t=11.76ns) -0.2 0.0 0.2 ns t top0 output data position 1 (t=11.76ns) t/7-0.2 t/7 t/7+0.2 ns t top6 output data position 2 (t=11.76ns) 2t/7-0.2 2t/7 2t/7+0.2 ns t top5 output data position 3 (t=11.76ns) 3t/7-0.2 3t/7 3t/7+0.2 ns t top4 output data position 4 (t=11.76ns) 4t/7-0.2 4t/7 4t/7+0.2 ns t top3 output data position 5 (t=11.76ns) 5t/7-0.2 5t/7 5t/7+0.2 ns t top2 output data position 6 (t=11.76ns) 6t/7-0.2 6t/7 6t/7+0.2 ns t tpll phase lock loop set 10.0 ms - 5 - receiver t rcp clk out period 11.76 t 50.0 ns t rch clk out high time 4t/7 ns t rcl clk out low time 3t/7 ns t rcd rclk+/- to clk out delay 5t/7 ns t rs ttl data setup to clk out 3t/7-2.5 ns t rh ttl data hold from clk out 4t/7-3.5 ns t tlh ttl low to high transition time 3.0 5.0 ns t thl ttl high to low transition time 3.0 5.0 ns t rip1 input data position 0 (t=11.76ns) -0.4 0.0 0.4 ns t rip0 input data position 1 (t=11.76ns) t/7-0.4 t/7 t/7+0.4 ns t rip6 input data position 2 (t=11.76ns) 2t/7-0.4 2t/7 2t/7+0.4 ns t rip5 input data position 3 (t=11.76ns) 3t/7-0.4 3t/7 3t/7+0.4 ns t rip4 input data position 4 (t=11.76ns) 4t/7-0.4 4t/7 4t/7+0.4 ns t rip3 input data position 5 (t=11.76ns) 5t/7-0.4 5t/7 5t/7+0.4 ns t rip2 input data position 6 (t=11.76ns) 6t/7-0.4 6t/7 6t/7+0.4 ns t rpll phase lock loop set 10 ms
clk in tx0-tx6 thine ac timing diagrams transmitter device note: 1) clk in: for THC63LVDM63A(r/f=gnd), denoted as solid line, for THC63LVDM63A(r/f=vcc), denoted as dashed line 2) vdiff = (ta+) - (ta-), .... (tclk+) - (tclk-) data valid t tcp t ts t t h 2.0v 0.8v 2.0v 0.8v 2.0v t tch 0.8v t tcl 2.0v tclk+ tx+/- tx6 tx5 tx4 tx3 tx2 tx1 tx0 vdiff=0v - 6 - 2.0v 0.8v 2.0v 0.8v t top0 t top6 t top5 t top4 t top3 t top2 t top1 t tcd
rx6 rx5 rx4 rx3 rx2 rx1 rx0 rx0-rx6 clk out thine ac timing diagrams receiver device data valid t r s t r h 2.0v 0.8v t rc p 2.0v 2.0v t rc h 0.8v 0.8v t rcl 2.0v rclk+ t rcd note: 1) vdiff = (ra+) - (ra-), .... (rclk+) - (rclk-) rx+/- vdiff=0v - 7 - t rip3 t rip4 t rip5 t rip6 t rip0 t rip1 t rip2 2.0v 0.8v
thine ac timing diagrams 5p f 100 w ta+ ta- vdiff = (ta+)-(ta-) lvds output load t lvt 80% 20% 80% 20% t lvt vdiff lvds output 8pf ttl output ttl output load 90% 10% t tcit 90% 10% t tcit clk in ttl input transmitter device transition times receiver device transition times ttl outpu t 80% 20% 80% 20% ttl output t tlh t thl receiver device transmitter device phase lock loop set time 2v 3.0v 3.6v /pdwn vcc clk in tclk+/- vdiff=0v t tpll 2v 3.0v 3.6v /pdwn vcc rclk+/- clk out 2v t rpll - 8 -
thine topshine taipei 114, taiwan, r. o. c. 5th. fi.,no. 68, chou-tze st.,nei hu dist., electronics corp. tel: 0 2 - 87 97 - 36 6 7 fax: 0 2 - 8 79 7 - 3 6 77
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